51²è¹Ý

T. Morris, S. Nair, “Key Protection for Private Computing on Public Platforms”, International Journal of Computer Science and Security (IJCSS). Volume 3, Issue 5. Pages 371-383. CSC Journals. Nov. 2009.

S. Abu-Nimeh, S. Nair, "Circumventing Security Toolbars and Phishing Filters via Rogue Wireless Access Points", The Journal of Wireless Communications and Mobile Computing, Wiley InterScience Journals, Vol. 9999, Jun. 2009.

S. Abu-Nimeh, D. Nappa, X. Wang, S. Nair, “Distributed Phishing Detection by Applying Variable Selection using Bayesian Additive Regression Trees”, IEEE International Conference on Communications (ICC 2009), Dresden, Germany, Jun. 2009.

T. Morris, S. Nair, “Private Computing on Public Platforms: Portable Application Security”, Wiley InterScience Journal of Wireless Communications and Mobile Computing. May 18, 2009.

T. Morris, S. Nair, “Encryption Key Protection for Private Computing on Public Platforms”, Proceedings of the Seventh Annual IEEE International Conference on Pervasive Computing and Communications (Percom 2009). Galveston, TX, USA. 9-13 March 2009.

T. Morris, S. Nair, “Private Computing on Public Platforms: Portable Application Security”, IEEE Global Communications Conference (GLOBECOM), Nov. 30- Dec. 4, 2008, Pages ECP.416:1-5.

S. Abu-Nimeh, S. Nair, "Bypassing Security Toolbars via DNS Poisoning", IEEE Global Communications Conference (GLOBECOM), Nov. 30- Dec. 4, 2008, Pages 1-6.

D. Easton, M. Thornton, S. Nair, S. Szygenda, “A Methodology for Disaster Tolerance Utilizing the Concepts of Axiomatic Design”, IIIS Journal of Systemics, Cybernetics and Informatics, 6(4), 2008, Pages 49-53.

J. Tian, S. Nair, L. Huang, N. Alaeddine, and M. Siok, "A Risk-Based Combined Approach to Achieving High Assurance", presentation at the Joint US/UK Workshop on Network-Centric Operation and Network Enabled Capability, Washington, DC, July 24-25, 2008.

S. Abu-Nimeh, D. Nappa, X. Wang, S. Nair, "A Distributed Architecture for Phishing Detection using Bayesian Additive Regression Trees", eCrime'08, 2008

M. Padmaraj, S. Nair, M. Marchetti, G. Chiruvolu, and M. Ali, “Bandwidth sensitive fast failure recovery scheme for metro Ethernet”, The International Journal of Computer and Telecommunications Networking, Elsevier Publications, Volume 52 , Issue 8 (June 2008) Pages 1603-1616

L. Huang X. Bai S. Nair, “Developing a SSE-CMM-based Security Risk Assessment Process for Patient-Centered Healthcare Systems”, 6th International Workshop on Software Quality, Leipzig, Germany, May, 2008

T. Morris, S. Nair, “Privacy Protected ELF for Private Computing on Public Platforms, IEEE International Conference on Availability, Reliability, and Security, March 2008.

S. Abu-Nimeh, D. Nappa, X. Wang, S. Nair, "Bayesian Additive Regression Trees-Based Spam Detection for Enhanced Email Privacy", In ARES '08: Proceedings of the 3rd International Conference on Availability, Reliability and Security, pages 1044-1051, 2008

D. Feinstein, S. Nair, M. Thornton, Advances in Quantum Computing Fault Tolerance and Testing, Proc. 10th IEEE High Assurance Systems Engineering Symposium (HASE 2007), Nov. 2007, Plano, Texas.

S. Abu-Nimeh, D. Nappa, X. Wang and S. Nair, Phishing Detection: An Experimental Study, ACM International Conference Proceeding Series; Vol. 269, Proc. of The 2nd APWG eCrime Researchers Summit, Pittsburg, PA, Oct. 2007, Pages 60-69.

D. Easton M. Thornton and V.S.S. Nair, Axiomatic Design Process for Disaster Tolerance, Proceedings of the 11th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI), July 8-11, 2007.

D. Easton, M. Thornton V.S.S. Nair, and J. Stracener, Axiomatic Design in the Biomedical Device Industry, Proceedings of the 11th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI), July 8-11, 2007.

T. Morris, V. S. S. Nair, “PCPP: On Remote Host Assessment via Naive Bayesian Classification”, IEEE, ACM International Parallel & Distributed Processing Symposium (IPDPS), International Workshop on Security in Systems and Networks, March 2007 Page(s):1 – 8

J. Kennington, V. S. S. Nair, and G. Spiride. Optimal spare capacity assignment for path restorable mesh networks: Cuts, decomposition, and an empirical analysis. International Journal on Parallel and Distributed Systems and Networks, Vol. 29, pages 170-179, 2007.

T. Morris, V. S. S. Nair, PCPP: Private Computing on Public Platforms, A New Paradigm in Public Computing, IEEE International Symposium on Wireless Pervasive Computing 2007, February 2007.

S. Nair, Ebru Celikel, Marco Marchetti, Adaptive Security and Reliability using Linear Erasure Correction Codes, Proceedings of 7th International Business Information Management Conference (7th IBIMA), Brescia, Italy, Dec,. 2006

S. Abu-Nimeh, S. Nair, "Phishing Attacks in a Mobile Environment", Mobile Antivirus Researchers Association (MARA), White Paper, 2006.

S. Abu-Nimeh, S. Nair, “Phishing the Airwaves: Phishing Wireless Devices”, The APWG (Anti-Phishing Working Group) 2006 Spring General Meeting and Email Authentication Summit in Chicago, IL.

M. Padmaraj, S. Nair, M. Marchetti, G. Chiruvolu, and M. Ali, "Distributed Fast Failure Recovery Scheme for Metro Ethernet", IEEE ICN, April 2006

S. Abu-Nimeh, S. Nair, and M. Marchetti, "An Experimental and Industrial Experience: Avoiding Denial of Service via Memory profiling", IEEE, AICCSA-06, March 2006

S. Abu-Nimeh, S. Nair, and M. Marchetti, "Avoiding Denial of Service via Stress-testing", IEEE, AICCSA-06, March, 2006

M. Ali, , G. Chiruvolu, A. Ge, M. Padmaraj, S. Nair, and M. Marchetti "Differentiated Survivability in Ethernet-Based MAN/WAN", IEEE AICCSA, March 2006

G. Deprez, M. Padmaraj, S. Nair, "Restoration Protocol for Heterogeneous Networks", IEEE AICCSA, March 2006

M. Ali, , G. Chiruvolu, M. Padmaraj, S. Nair, and M. Marchetti "Augmented Hose Model for Metro Ethernet", In proceedings of IEEE ICON, November 2005

M. Padmaraj, S. Nair, M. Marchetti, G. Chiruvolu, and M. Ali, "Simulation of recovery scheme for Metro Ethernet", In Proceedings of OPNETWORKS'05, August 2005

G. Deprez, M. Padmaraj, S. Nair, "Net Planner: A Capacity Allocation Tool", Telecommunications, 2005. ConTEL 2005. Proceedings of the 8th International Conference on Volume 1, June 15-17, 2005 Page(s):147 - 154

M. Padmaraj; S. Nair; M. Marchetti; G. Chiruvolu; M. Ali; A. Ge; "Metro Ethernet traffic engineering based on optimal multiple spanning trees", Wireless and Optical Communications Networks, 2005. WOCN 2005. Second IFIP International Conference on 6-8 March 2005 Page(s):568 - 572

M. Padmaraj, S. Nair, M. Marchetti, G. Chiruvolu, M. Ali. "Traffic Engineering in Enterprise Ethernet with Multiple Spanning Tree Regions," icw, pp. 261-266, 2005 Systems Communications (ICW'05, ICHSN'05, ICMCS'05, SENET'05), 2005.

K. Indiradevi and V. S. S. Nair. Simulation based validation of authentication protocols. SDPS Transactions on Integrated Design and Process Science, Vol 8., Issue 4, pp. 79-98, Dec. 2004.

M. Stephens and S. Nair, Providing Service Level Agreements for Idle CPU Cycles from an Internet PC Grid, 16th IASTED International Conference on Parallel and Distributed Computing and Systems, PDCS 2004, November 9-11, 2004, Cambridge, MA, USA.

M. Stephens and S. Nair, Internet Distributed Computing for e-Business, Proceedings of the Seventh International Conference on Electronic Commerce Research, pp. 221 – 233, Jun. 2004.

V. Venkataraghavan, S. Nair, P. Seidel, Test Case Generation for the Validation of Properties in Security Protocol Implementation, The South Central Security Symposium, Jun. 2004

M. Padmaraj and S. Nair. Simulation of meta-authentication protocol for secure grid computing. In Proceedings of OPNETWORKS '03. MIL 3, Aug. 2003.

M. Padmaraj, V. Venkataraghavan, and S. Nair. Simulation of network security protocols. In Proceedings of OPNETWORKS '02. MIL 3, 2002.

K. Indiradevi, V. S. S. Nair, and J. A. Abraham. A meta-authentication framework for secure authentication protocols. Infrastructure for e-Business, e-Education, and e-Science on the Internet, SSGRR-2001, Italy, Aug. 2001.

K. Pillai, V. S. S. Nair, Software Development Management, Wiley Encyclopedia of Electrical and Electronic Engineering (J. B. Webster Editor), John Wiley & Sons Inc. 2000, ISBN 0-471-35895-9

H. C. Cankaya and V. S. S. Nair. SONSAT: a reliability analysis tool for SONET networks. In Proceedings of the IEEE ASSET'00 Symposium, June 2000.

H. C. Cankaya and V. S. S. Nair. Improved survivability analysis of SONET SHRs. International Journal of Computer and Telecommunications Networking, 31:2505-2528, Dec. 1999.

J. L. Kennington, V. S. S. Nair, and M. H. Rahman. Optimization based algorithms for finding minimal cost ring covers in survivable networks. Journal of Computational Optimization and Applications, 14:219-230, Oct. 1999.

K. Indiradevi, V. S. S. Nair, and J. A. Abraham. Formal verification of authentication protocols. In Proceedings of the IEEE ASSET'99 Symposium, Richardson, TX. IEEE, Jul. 1999.

Z. Alkhalifa and V. S. S. Nair. Linear codes for end to end cell loss recovery in VBR video transmission over ATM networks. IEEE International Conference on ATM '99, June 1999.

Z. Alkhalifa, V. S. S. Nair, N. Krishnamurthy, and J. A. Abraham. Design and evaluation of system-level checks for on-line error detection in real-time systems. IEEE Transactions on Parallel and Distributed Systems, June 1999.

G. Spiride and V. S. S. Nair. A decomposition approach for modular spare capacity allocation in telecommunication networks. In INFORMS meeting in Cincinnati, May 1999.

M. A. Thornton and V. S. S. Nair. Behavioral synthesis of combinational logic using spectral-based heuristics. ACM Transactions on Design Automation of Electronic Systems, 4, no. 2:219-230, Apr. 1999

H. C. Cankaya and V. S. S. Nair. Hierarchical approach to performance analysis of self-healing SONET networks. In IEEE Proceedings of the Seventh International Conference on Computer Communications and Networks, pages 362-69. IEEE Comp. Soc., 1998.

H. C. Cankaya and V. S. S. Nair. Survivability analysis of self-healing SONET rings. In IEEE Proceedings of GLOBECOM'98, volume 4, pages 2276-81. IEEE Com. Soc., 1998.

H. C. Cankaya and V. S. S. Nair. Accelerated reliability analysis for self-healing SONET networks. ACM Computer Communications Review, 28(4):268-77, October 1998.

K. Indiradevi and V. S. S. Nair. Evaluation of a new signaling protocol for wireless ATM LANs. In Proceedings of the 6th International Conference on Telecommunication Systems, Nashville, TN, 1998.

G. Spiride, H. C. Cankaya, G. I. Indiradevi, S. Nair, and N. Stollon. Performance evaluation of a round robin arbiter for a hybrid slotted bus. In Proceedings of OPNETWORKS '98. MIL 3, 1998.

G. Spiride and V. S. S. Nair. Performance evaluation for restoration protocols for SONET mesh networks. In Proceedings of OPNETWORKS '98. MIL 3, 1998.

G. Spiride and V. S. S. Nair. Simulation study for a SONET restoration protocol - extended abstract. In Proc. of the 28th FTCS conf., 1998.

G. Spiride and S. Nair. Modeling and simulation of restoration protocols for SONET mesh networks. In Proc. of the IEEE Global Telecomm. Conf. (GLOBECOM), pages 1538-1543, 1998.

V. S. S. Nair and Z. Alkhalifa. Linear codes for erasure error correction (lec). 5th IEEE International On-Line Testing Workshop, July 1998.

H. Kim and V. S. S. Nair. Software fault tolerance for distributed object-based computing. The Journal of Systems and Software, Vol. 39, No.2, pp. 103-117, Nov. 1997.

H. C. Cankaya and V. S. S. Nair. Survivability metrics for self-healing SONET mesh networks. In Proceedings of ISCIS'XII, volume 1, pages 269-276. Bogazici University, Bogazici University Press, 1997.

H. C. Cankaya and V. S. S. Nair. Reliability and availability evaluation of self-healing SONET mesh networks. In IEEE Proceedings of GLOBECOM'97, volume 1, pages 252-256. IEEE Com. Soc., 1997.

Z. Alkhalifa and V. S. S. Nair. Design and implementation of a portable control-flow checking technique. IEEE International Workshop on High Assurance Systems Engineering, Aug. 1997.

K. Pillai and V. S. S. Nair. A composite model for early software cost prediction. IEEE Transactions on Software Engineering, 23, no. 8:485-497, Aug. 1997.

K. Pillai and V. S. S. Nair. Statistical analysis of non-stationary software metrics Journal of Information and Software Technology, 39, no.5:363-373, July, 1997.

V. S. S. Nair. Application layer techniques for hardware and software fault tolerance. Proceedings of the Second World Conference on Integrated Design and Process Technology (IDPT), pages 138-145, Dec. 1996.

K. Pillai, V. S. S. Nair, H. Cropper, and R. Zajac. A configuration management system with evolutionary prototyping. ISACC '96, Applications and Research in Software Engineering, Management Information Systems and Distributed Computing Systems, pages 3-11, Oct. 1996.

K. Kanawati, N. Krishnamurthy, S. Nair, and J. A. Abraham. Evaluation of integrated system-level checks for on-line error detection. IEEE International Computer Performance and Dependability Symposium, Sep. 1996.

V. S. S. Nair, H. Kim, N. Krishnamurthy, and J. A. Abraham. Design and evaluation of automated high-level checks for signal processing applications. Proceedings of SPIE Advanced Algorithms and Architectures for Signal Processing Conference, pages 292-301, Aug. 1996.

B. Kapoor and V. S. S. Nair. Improving path sensitizability of combinational circuits. VLSI Design Journal, 5:49-57, 1996.

V. S. S. Nair, J. A. Abraham, and P. Banerjee. Efficient techniques for the analysis of algorithm-based fault tolerance schemes. IEEE Transactions on Computers, pages 499-503, Apr. 1996.

M. Thornton and V. S. S. Nair. BDD-based spectral approach for Reed-Muller circuit realization. IEE Proceedings - Computers and Digital Techniques, 143:145-150, Mar. 1996.

V. S. S. Nair, K. Indiradevi, and J. A. Abraham. Formal checking of reliable user interfaces. Proceedings of IEEE International Conference on Fault-Tolerant Systems, pages 17-25, Dec. 1995.

M. Thornton and V. S. S. Nair. Efficient calculation of spectral coefficients and their applications. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 14:1328-1341, Nov. 1995.

K. Indiradevi and V. S. S. Nair. Usability and reliability evaluation of user interfaces. Proceedings of IEEE International Workshop on Evaluation Techniques for Dependable Systems, Oct. 1995.

L. Mcfearin and V. S. S. Nair. Control-flow checking using assertions. Proceedings of IFIP International Working Conference on Dependable Computing for Critical Applications, pages 103-112, Sep. 1995.

C. F. Salviano and V. S. S. Nair. One-for-many: A design pattern for a piecemeal programming language extension through one-to-many translation. Proceedings of Second Annual Conference on the Pattern Languages of Programs, pages 1-9, Sep. 1995.

M. Thornton and V. S. S. Nair. Fast Reed-Muller spectrum computation using output probabilities. IFIP WG 10.5 Workshop on Applications of Reed-Muller Expansion in Circuit Design, pages 281 - 287, Aug. 1995.

H. Kim and V. S. S. Nair. Application layer software fault tolerance for distributed object-oriented systems. IEEE International Conference on Computer Software and Applications (COMPSAC-95), pages 235-241, Aug. 1995.

M. Thornton and V. S. S. Nair. Parity function detection and realization using a small set of spectral coefficients. Proceedings of IEEE/ACM International Workshop on Logic Synthesis (IWLS), pages 8.39 - 8.47, May 1995.

C. Erbas, M. Tanik, and V. S. S. Nair. Parallel memory allocation and data alignment in SIMD machines. Journal on Parallel Algorithms and Applications, 4:139-151, Dec. 1994.

M. A. Thornton and V. S. S. Nair. Efficient spectral coefficient calculation using circuit output probabilities. Digital Signal Processing: A Review Journal, pages 245-254, Oct. 1994.

B. Kapoor and V. S. S. Nair. An efficient tree-based algorithm for computing path delay fault coverage. Proceedings of IEEE International ASIC Conference, pages 417-420, Sep. 1994.

B. Kapoor and V. S. S. Nair. Computing exact path delay fault coverage using OBDDs. Proceedings of IEEE Midwest Symposium on Circuit and Systems, Aug. 1994.

V. S. S. Nair and S. Venkatesan. Algorithm-based fault tolerance for non-computationally intensive applications. Proceedings of SPIE Advanced Algorithms and Architectures for Signal Processing Conference, pages 751-759, Jul. 1994.

R. Rowell and V. S. S. Nair. SELAC - statistical error location and correction in secondary memory systems. Journal of Micro Computer Applications, 17:255-271, Jun. 1994.

M. A. Thornton and V. S. S. Nair. Behavioral to structural translation in ESOP form. Proceedings of IEEE International Verilog HDL Conference, pages 58-62, Mar. 1994 (Best Paper Award).

B. Kapoor and V. S. S. Nair. Area, performance, and sensitizable paths. Proceedings of 4th IEEE Great Lake Symposium on VLSI, pages 222-227, Mar. 1994.

R. Rowell and V. S. S. Nair. Secondary storage error correction utilizing inherent redundancy of stored data. Proceedings of IFIP Working Conference on Dependable Computing for Critical Applications (DCCA), Jan. 1994.

C. Erbas, M. Tanik, and V. S. S. Nair. Storage schemes for parallel memory systems: An approach based on circulant matrices. Proceedings of IEEE Symposium on Parallel and Distributed Processing (SPDP), pages 92-99, Dec. 1993.

S. Krishna, T. Diamond, and V. S. S. Nair. Hierarchical object oriented approach to fault tolerance in distributed systems. Proceedings of IEEE International Symposium on Software Reliability Engineering, pages 168-177, Nov. 1993.

M. A. Thornton and V. S. S. Nair. An iterative combinational logic synthesis technique using spectral information. Proceedings of IEEE European Design Automation Conference (EURO-DAC), pages 358-363, Sep. 1993.

M. A. Thornton and V. S. S. Nair. A numerical method for Reed-Muller circuit synthesis. Proceedings of IFIP Workshop on Applications of the Reed-Muller Expansion in Circuit Design, pages 69-74, Sep. 1993.

B. Kapoor and V. S. S. Nair. Heuristics for Shannon decomposition in area-efficient realization of fully robust path delay fault testable digital logic. Proceedings of IEEE International Workshop on Logic Synthesis (IWLS), pages 4c1-4c8, May 1993.

V. S. S. Nair, Y. V. Hoskote, and J. A. Abraham. Probabilistic evaluation of on-line checks in fault-tolerant multiprocessor systems. IEEE Transactions on Computers, 41:532-541, May, 1992.

P. Banerjee, J. Rahmeh, C. Stunkel, V. S. S. Nair, K. Roy, and J. A. Abraham. Algorithm-based fault tolerance on a hypercube multiprocessor. IEEE Transactions on Computers, pages 1132-1145, Sep. 1990.

V. S. S. Nair and J. A. Abraham. A new probabilistic model for the analysis of fault-tolerant systems using concurrent error detection. Proceedings of SPIE Advanced Algorithms and Architectures for Signal Processing Conference, Jul. 1990.

V. S. S. Nair and J. A. Abraham. Hierarchical design and analysis of fault-tolerant multiprocessor systems using concurrent error detection. Proceedings of the 20th IEEE International Symposium on Fault-Tolerant Computing, pages 130-137, Jun. 1990.

V. S. S. Nair and J. A. Abraham. Real number codes for fault-tolerant matrix operations on processor arrays. IEEE Transactions on Computers, pages 426-435, Apr. 1990.

V. S. S. Nair and J. A. Abraham. A model for the analysis, design and comparison of fault-tolerant WSI architectures. Proceedings of IFIP Workshop on Wafer Scale Integration, pages 99-108, June 1989.

V. S. S. Nair and J. A. Abraham. A model for the analysis of fault-tolerant signal processing architectures. Proceedings of SPIE Advanced Algorithms and Architectures for Signal Processing Conference, pages 246-257, Aug. 1988.

P. Banerjee, J. T. Rahmeh, C. B. Stunkel, V. S. S. Nair, K. Roy, and J. A. Abraham. An evaluation of system-level fault tolerance on the Intel hypercube multiprocessor. Proceedings of the 18th IEEE International Symposium on Fault-Tolerant Computing, pages 362-367, Jun. 1988.

V. S. S. Nair and J. A. Abraham. General linear codes for fault-tolerant matrix operations on processor arrays. Proceedings of the18thIEEE International Symposium on Fault-Tolerant Computing, pages 180-185, Jun. 1988.

V. S. S. Nair and J. A. Abraham. Average checksum codes for fault-tolerant matrix operations on processor arrays. Proceedings of the International Conference on Supercomputing, 3:284-290, May, 1987.